16E1 Plesiochronous Digital Hierarchy

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16E1 Plesiochronous Digital Hierarchy
Posting date : Sep 18, 2007
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85-
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16E1 PDH is the multiservice fiber transmission system based on FPGA chip, the chip adopts jitter reduced, digital phase locked and clock distilled, E1 anti-jamming technology. The inner software and hardware are of modular design, integrating coding, decoding, message insertion and alarm, and make the circuit simple so as to improve the reliability of the device. It is ideal for the situations that atrocious environment, highly requested reliability and completely auxiliary functions, such as: Mobile, Unicom, Telecom, Electric Power, Police, Army, Highway, Aviation special communication networks etc. Feature: Offer 16E1(2.048Mbps)interfaces, feature unbalanced interface(BNC) and balanced interface(RJ45) Offer an official phone interface, not occupy E1 channel Full LED indicators and voice alarm display local and remote status Jitter tolerance and jitter transmission characteristic of E1 channel have high performance, which is superior to industry standard Integrated hardware circuits, low power consumption Dual power supplies backup The circuit is designed simply, the device works steadily Highly integrated hardware circuit, power consumption is less than 15W

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